User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 289 of 909 2019 Ambiq Micro, Inc.
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8.15.2.3 FIFOTHR Register
FIFO Threshold Configuration
OFFSET: 0x00000104
INSTANCE 0 ADDRESS: 0x50004104
INSTANCE 1 ADDRESS: 0x50005104
INSTANCE 2 ADDRESS: 0x50006104
INSTANCE 3 ADDRESS: 0x50007104
INSTANCE 4 ADDRESS: 0x50008104
INSTANCE 5 ADDRESS: 0x50009104
Sets the threshold values for incoming and outgoing transactions. The threshold values are used to
assert the interrupt if enabled, and also used during DMA to set the transfer size as a result of DMATHR
trigger.
Table 398: FIFOPTR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FIFO1REM FIFO1SIZ FIFO0REM FIFO0SIZ
Table 399: FIFOPTR Register Bits
Bit Name Reset RW Description
31:24 FIFO1REM 0x0 RO
The number of remaining data bytes slots currently in FIFO 1 (written by
interface, read by MCU)
23:16 FIFO1SIZ 0x0 RO
The number of valid data bytes currently in FIFO 1 (written by interface,
read by MCU)
15:8 FIFO0REM 0x0 RO
The number of remaining data bytes slots currently in FIFO 0 (written by
MCU, read by interface)
7:0 FIFO0SIZ 0x0 RO
The number of valid data bytes currently in the FIFO 0 (written by MCU,
read by interface)
Table 400: FIFOTHR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD FIFOWTHR
RSVD
FIFORTHR