User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 281 of 909 2019 Ambiq Micro, Inc.
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Figure 41showstheoperationofflowcontrolinthemiddle ofareadtransfer.IRQmustbedeasserted
aftertheleadingedgeofSCKonthefirstbitofthebyte(labelled7)andbeforethefallingedgeofthe7
th
bit of the byte (labelled 1) in order to insure that SCK stops at the end of the byte. Deasserting IRQ
outside of that window can produce unpredictable results. SCK will resume at some point after the
assertionofIRQ.
8.13 Pre-read Control
The STARTRD field defines the number of bus clock cycles before the end of each byte where the IO read
request occurs. For all I2C frequencies and SPI frequencies below 16 MHz, the STARTRD field should be
set to 0 to minimize the potential of the IO transfer holding off a bus access to the FIFO. For SPI
frequencies of 16 MHz or 24 MHz, the STARTRD field must be set to a value of 2 to insure enough time for
the IO preread.
8.14 Minimizing Power
Each I
2
C/SPI Master has a global interface enable bit REG_IOMSTRn_IOMCFG_IFCEN. This bit should
be kept at 0 whenever the interface is not being used in order to minimize power consumption. The FIFO
Figure 40. Flow Control in the Middle of a Write Transfer
SCK
nCE
MOSI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4
MISO/IRQ
Window
Figure 41. Flow Control in the Middle of a Read Transfer
SCK
nCE
MOSI
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4
IRQ
MISO
Window