User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 280 of 909 2019 Ambiq Micro, Inc.
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Flowcontrolmaybeassertedeitherpriortothefirstbytetransfer,whichwilldelay thestartofSCK,or
withineachbytetransferred,whichwillpauseSCKattheendofthatbyte.Theexamplesbelowassume
thatWTFCPOLorRDFCPOLaresetto0.
Figure 38 shows the operation of flow control at the beginning of a write transfer or a normal read
transfer which begins with an offset byte write. Either MISO or IRQ (selected by WTFCIRQ)  must be
deassertedlowwithin½oftheSCKperiodafternCEisassertedlowinordertodelay
theclock.SCKwill
continueinitsinactivestateuntilMISOorIRQischangedtotheactivestate,andthenwillbeginnormal
operation.
Figure 39 shows the operation of flow control at the beginning of a raw read transfer. IRQ must be
deassertedlowwithin½oftheSCKperiodafternCE
isassertedlowinordertodelaytheclock.SCKwill
continue in its inactive state until IRQ is changed to the active state, and then will begin normal
operation.
Figure 40shows theoperation offlowcontrolin the middle ofa write transfer. MISO orIRQ must be
deassertedafterthe
leadingedgeofSCKonthe first bit ofthebyte(labelled7)andbeforethefalling
edge of the 7
th
 bit of the byte (labelled 1) in order to insure that SCK stops at the end of the byte.
DeassertingMISOorIRQoutsideofthatwindowcanproduceunpredictableresults.SCKwillresumeat
somepointaftertheassertionofMISOorIRQ.
SCK
nCE
MISO/IRQ
MOSI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4
Figure 38. Flow Control at Beginning of a Write Transfer
Figure 39. Flow Control at Beginning of aRawReadTransfer
SCK
nCE
MISO
MOSI
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4
IRQ