User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 278 of 909 2019 Ambiq Micro, Inc.
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Figure 37. SPI CPOL and CPHA
If CPOL is 0, the clock SCK is normally low and positive pulses are generated during transfers. If CPOL is
1, SCK is normally high and negative pulses are generated during transfers.
If CPHA is 0, the data on the MOSI and MISO lines is sampled on the edge corresponding to the first SCK
edge after nCE goes low (i.e. the rising edge if CPOL is 0 and the falling edge if CPOL is 1). Data on MISO
and MOSI is driven on the opposite edge of SCK.
If CPHA is 1, the data on the MOSI and MISO lines is sampled on the edge corresponding to the second
SCK edge after nCE goes low (i.e. the falling edge if CPOL is 0 and the rising edge if CPOL is 1). Data on
MISO and MOSI is driven on the opposite edge of SCK.
The SPOL and SPHA bits may be changed between Commands if different slave devices have different
requirements. In this case the IFCEN bit should be set to 0 either before or at the same time as SPHA and
SPOL are changed, and then set back to 1 before CMD is written.
8.9 Repeating a Command
Some peripherals, particularly sensors such as accelerometers and gyroscopes, have multiple registers
which hold sample data (2 bytes each of X, Y and Z are common), and FIFOs behind these registers which
hold multiple samples. In order to allow software to retrieve several samples with a single operation, the
Apollo3 Blue MCU I
2
C/SPI Master includes the capability to execute the same Command multiple times. If
multiple Commands are desired, the REG_IOMSTRn_CMDRPT Register is loaded with the number of
additional times to execute the next Command (e.g. loading CMDRPT with the value 3 will cause the next
Command to be executed a total of 4 times). When a Command is written to the Command Register, the
Command is then executed multiple times, filling or emptying the FIFO as appropriate. The series of
repeated Commands behaves as if it was a single long Command, with a single CMDCMP interrupt
occurring at the end and THR interrupts occurring if the FIFO crosses the relevant threshold. At the end of
any Command the CMDRPT Register has the value 0, so that single Commands may always be executed
without requiring a write to CMDRPT.
As an example, assume the peripheral has 6 bytes of sensor sample data located at register offsets 10, 11,
12, 13, 14 and 15. Also assume the internal FIFO threshold of the peripheral has been set so that an
interrupt occurs when the FIFO contains 8 samples. The CMDRPT register is set to 7, and a read
CPOL=0
CPOL=1
7 6 1
MOSI
0 7 6 1 0X 5 4 3 2 5 4 3 2
7 6 1
MISO
0 7 6 1 0X 5 4 3 2 5 4 3 2
SCK
7 6 1
MOSI
0 7 6 1 0X 5 4 3 2 5 4 3 2
7 6 1
MISO
0 7 6 1 0X 5 4 3 2 5 4 3 2
CPHA=0
CPHA=1
X
X
X
X
SCK
nCE