User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 274 of 909 2019 Ambiq Micro, Inc.
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important for slave devices which do not support an Address Pointer architecture. For devices which do
include an Address Pointer, multiple Raw Reads may be executed after a Normal Read to access
subsequent registers as the Address Pointer increments, without having to execute the Offset Address
Transmission for each access.
Figure 31. I
2
C Raw Read Operation
8.7.12 Holding the Interface with CONT
In all of the previously described transactions, the I
2
C/SPI Master terminates the I
2
C operation with a
STOP sequence. In environments where there are other masters connected to the I
2
C interface, it may be
necessary for the Apollo3 Blue MCU to hold the interface between Commands to insure that another
master does not inadvertently access the same slave that the Apollo3 Blue MCU is accessing. In order to
implement this functionality, the CONT bit should be set in the CMD Register. This will cause the I
2
C/SPI
Master to keep SDA high at the end of the transfer so that a STOP does not occur, and the next transaction
begins with a RESTART instead of a START. Note that for a Normal Read the interface is held between the
Offset Address Transmission and the actual read independent of the state of CONT, but it CONT is set the
read transaction will not terminate with a STOP.
8.7.13 I
2
C Multi-master Arbitration
The Apollo3 Blue MCU I
2
C/SPI Master supports multi-master arbitration in I
2
C mode. There are two cases
which must be handled.
The first is the case where another master initiates an I
2
C operation when the Apollo3 Blue MCU Master is
inactive. In this case the I
2
C/SPI Master will detect an I
2
C START operation on the interface and the
START interrupt will be asserted, which tells the software not to generate any IO operations (which will not
be executed in any case). Software then waits for the STOP interrupt, which reenables operation.
The second case is where another master initiates an operation at the same time as the Apollo3 Blue
MCU. In this case there will be a point where one master detects that it is not driving SDA low but the bus
signal is low, and that master loses the arbitration to the other master. If the Apollo3 Blue MCU I
2
C/SPI
Master detects that it has lost arbitration, it will assert the ARB interrupt and immediately terminate its
operation. Software must then wait for the STOP interrupt and re-execute the current Command.
8.8 SPI Operations
8.8.1 SPI Configuration
The I
2
C/SPI Master supports all combinations of the polarity (CPOL) and phase (CPHA) modes of SPI
using the REG_IOMSTRn_IOMCFG_SPOL and REG_IOMSTRn_IOMCFG_SPHA bits. It also may be
configured in either 3-wire or 4-wire mode. In 4-wire mode, the MOSI and MISO interface signals use
separate IO pins. In 3-wire mode, MOSI and MISO are multiplexed on a single IO pin for more efficient pin
utilization. The 3/4 wire configuration is selected in the mapping function of the PINCFG module.
SDA
SCL
7 0
Byte N
A 7 0
Byte N+1
NAddr AR