User Manual

ManualsBrandsSparkFun Electronics ManualsDevelopment Boards & KitsApollo3 Blue Edge Development Board

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 27 of 909 2019 Ambiq Micro, Inc.

Table 596: UART1 RTS Configuration .................................................................................... 403

Table 597: UART1 CTS Configuration .................................................................................... 403

Table 599: PDM DATA Configuration .................................................................................... 404

Table 600: I2S BCLK Configuration ........................................................................................ 404

Table 601: I2S WCLK Configuration ...................................................................................... 404

Table 598: PDM CLK Configuration ....................................................................................... 404

Table 603: Secure Card Clock Configuration ........................................................................... 405

Table 604: Secure Card IO Configuration ................................................................................ 405

Table 605: Secure Card RST Configuration ............................................................................. 405

Table 602: I2S DAT Configuration .......................................................................................... 405

Table 606: CLKOUT Configuration ......................................................................................... 406

Table 607: 32kHz CLKOUT Configuration ............................................................................. 406

Table 608: ADC Analog Input Configuration .......................................................................... 406

Table 609: ADC Trigger Input Configuration .......................................................................... 407

Table 610: Voltage Comparator Reference Configuration ....................................................... 407

Table 611: Voltage Comparator Input Configuration ............................................................... 407

Table 612: SWO Configuration ................................................................................................ 408

Table 613: FASTGPIO Register Map ...................................................................................... 409

Table 614: BBVALUE Register ............................................................................................... 410

Table 615: BBVALUE Register Bits ........................................................................................ 410

Table 616: BBSETCLEAR Register ........................................................................................ 410

Table 617: BBSETCLEAR Register Bits ................................................................................. 411

Table 618: BBINPUT Register ................................................................................................. 411

Table 619: BBINPUT Register Bits ......................................................................................... 411

Table 620: DEBUGDATA Register ......................................................................................... 412

Table 621: DEBUGDATA Register Bits .................................................................................. 412

Table 622: DEBUG Register .................................................................................................... 412

Table 623: DEBUG Register Bits ............................................................................................. 412

Table 624: GPIO Register Map ................................................................................................ 414

Table 625: PADREGA Register ............................................................................................... 417

Table 626: PADREGA Register Bits ........................................................................................ 417

Table 627: PADREGB Register ............................................................................................... 419

Table 628: PADREGB Register Bits ........................................................................................ 420

Table 629: PADREGC Register ............................................................................................... 422

Table 630: PADREGC Register Bits ........................................................................................ 422

Table 631: PADREGD Register ............................................................................................... 424

Table 632: PADREGD Register Bits ........................................................................................ 425

Table 633: PADREGE Register ............................................................................................... 427

Table 634: PADREGE Register Bits ........................................................................................ 427

Table 635: PADREGF Register ................................................................................................ 429

Table 636: PADREGF Register Bits ........................................................................................ 429

Table 637: PADREGG Register ............................................................................................... 432

Table 638: PADREGG Register Bits ........................................................................................ 432

Table 639: PADREGH Register ............................................................................................... 434

Table 640: PADREGH Register Bits ........................................................................................ 434

Table 641: PADREGI Register ................................................................................................. 437