User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 269 of 909 2019 Ambiq Micro, Inc.
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frequency of 1.2 kHz. If TOTPER division is enabled by REG_IOMSTRn_CLKCFG_DIVEN, the length of
the low period of the clock is specified by REG_IOMSTRn_CLKCFG_LOWPER + 1. Otherwise, the clock
will have a 50% duty cycle.
Figure 22. I
2
C/SPI Master Clock Generation
8.5 Command Operation
In order to minimize the amount of time the CPU must be awake during I
2
C/SPI Master operations, the
architecture of the I
2
C/SPI Master is organized around processing commands which transfer data to and
from an internal 64-byte FIFO.
The IOMn_CMD Register in “IOM Registers” on page 282 is used for command operations for both the SPI
and I2C communication channels.
For writes to the interface, software writes data to the FIFO (REG_IOMn_FIFO_FIFO) and then sends a
single command to the REG_IOMn_CMD Register. Unless the TSIZE field of the CMD is zero, at least one
word (4 bytes) of data must be written into the FIFO prior to writing the CMD Register or an ICMD interrupt
will be generated and the operation will be terminated.The Command includes either the I
2
C slave address
or the SPI channel select, the desired address offset and the length of the transfer. At that point the I
2
C/SPI
Master executes the entire transfer, so the CPU can go to sleep. If more than 128 bytes are to be
transferred, the Master will generate a THR interrupt when the FIFOSIZ value,
REG_IOMn_FIFOPTR_FIFOSIZ, drops below the write threshold REG_IOMn_FIFOTHR_FIFOWTHR so
the CPU can wake up and refill the FIFO. The I
2
C/SPI Master will generate the CMDCMP interrupt when
the command is complete. In each case, the total number of bytes transferred in each operation is
specified in the LENGTH field of the CMD Register. If software executes a write to the FIFO when it is full
(FIFOSIZ is greater than 124) the FOVFL interrupt will be generated and the transfer will be terminated.
For reads, the CMD Register is first written with the command and the CPU can go to sleep. The Master
initiates the read and transfers read data to the FIFO. If the FIFOSZ value exceeds the read threshold
REG_IOMn_FIFOTHR_FIFORTHR, a THR interrupt is generated so the CPU can wake up and empty the
FIFO. A CMDCMP interrupt is also generated when the Command completes. If software executes a read
from the FIFO when it has less than a word of data the FUNDFL interrupt will be generated and the
transfer will be terminated. FUNDFL will not be generated if the read transfer has already completed, so
that software can read the last FIFO word even if it is incomplete.
If the FIFO empties on a write or fills on a read, the I
2
C/SPI Master will simply pause the interface clock
until the CPU has read or written a byte from the FIFO. This avoids the requirement that the thresholds be
set conservatively so that the processor can wake up fewer times on long transfers without a risk of an
underflow or overflow aborting a transfer in progress.
If software initiates an incorrect operation, such as attempting to read the FIFO on a write operation or
when it is empty, or write the FIFO on a read operation or when it is full, the Master will generate an IACC
24 MHz
768 kHz
...
CLKCTR
LOWCMP
TOTCMP
CLKFF
Set
Clr
IFC_CLK
FSEL
DIV3
DIV3
DIVEN
48 MHz