User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 266 of 909 2019 Ambiq Micro, Inc.
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Figure 20. IOM Pause Example
Each pause source is independently enabled via the REG_IOM_PAUSEEN register. In addition to
independent enable of the pause bits, there is also independent control of which pause event will signal a
CQPAUSE interrupt. This is controlled through the REG_IOM_CQFLAGS.CQIRQMASK field.
There are 16 possible pause sources. When the value of the pause source is set, and the pause is
enabled in the REG_IOM_PAUSEEN register, the CQ will stop fetching. The REG_IOM_CQADDR is
updated after each fetch, and when paused, will point to the next doublet to be fetched when the pause
condition is removed. The connection of the pause bits are shown below. The SW Flags are accessed via
the IOM_CQSETCLEAR register.
ADDRESS1
WRITEDATA1
ADDRESS2
WRITEDATA2
ADDRESS3
WRITEDATA3
ADDRESS4
WRITEDATA4
CQBUFF ER
ADDRESS10
WRITEDATA10
CQFETCHAN DWRITE1 CQFETCHAN DWRITE2
Writewhichcauses
PAUSE event
CQFETCHANDWRITE4
CQFETCHAN DWRITE10
(CQENOFF/DISABLE)
TIME
CQPAUSED
EXTERNALEVENT/
WRITETOREMOVE
PAUSECONDITION
GPIO
Software
MSPI
BLE
OtherIOM
IOMPAUSEEXAMPLE