User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 260 of 909 2019 Ambiq Micro, Inc.
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IO_CLK is used as the source of the interface clock and has selectable frequencies. The overview of the
clocking structure is shown below:
Figure 15. Clocking Structure for IOM Module
The APB_CLK is an internal clock sourced from the bus fabric and operates at a fixed 24MHz frequency. It
is used for internal communication and is heavily clock gated to reduce dynamic power.
The IO_CLK is generated within the central clocking module and enabled through the
REG_IOM_CLKCFG.IOCLKEN field. This clock must be enabled by software prior to module operation.
The primary frequency of the IO_CLK is selected via the REG_IOM_CLKCFG.FSEL field, and further
divided by either or both of the internal divide by 3 divider (enabled via the REG_IOM_CLKCFG.DIV3
field), or a programmable divider (enabled by REG_IOM_CLKCFG.DIVEN and division set by
REG_IOM_CLKCFG.TOTPER and REG_IOMCLKCFG.LOWPER fields) as shown below.
HFRC
DMA
Fabric
IOM
IOM REGSIOM REGSIOM REGS
FIFO
APB
IFACE
APB
IFACE
DMA
I2C
SPI
PIN 
MUX
IOM
CLKGEN
IFC_CLK
IOM
IOM REGS
FIFO
APB
IFACE
DMA
I2C
SPI
PIN 
MUX
IOM
CLKGEN
IFC_CLK
IO_CLK
IOM
MODULE
FSEL
CL K EN
RI PPLE
DIVIDERS
CL K G EN
RI PPLE
DIVIDERS
CL K G EN