User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 258 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
8. I
2
C/SPI Master Module
Figure 14. Block Diagram for the I
2
C/SPI Master Module
8.1 Functional Overview
The Apollo3 Blue MCU includes six I
2
C/SPI High Speed Master Modules, shown in Figure 14, each of
which functions as the Master of an I
2
C or SPI interface as selected by the
REG_IOMSTRn_IOMCFG_IFCSEL bit (n=0 or 1). A 64-byte bidirectional FIFO and a sophisticated
Command mechanism allow simple initiation of I/O operations without requiring software interaction.
In I
2
C mode the I
2
C/SPI Master supports 7- and 10-bit addressing, multi-master arbitration, interface
frequencies from 1.2 kHz to 1.0 MHz and up to 255-byte burst operations. In SPI mode the I
2
C/SPI Master
supports up to 4 slaves with automatic nCE selection, 3 and 4-wire implementation, all SPI polarity/phase
combinations and up to 4095-byte burst operations, with both standard embedded address operations of
up to 3 bytes and raw read/write transfers. Interface timing limits are as specified in Table 1155 on
page 788 and Table 1156 on page 789.
The active interface is selected by enabling the module enable bit for the interface in the
REG_IOMn_SUBMODCTL. Only one interface can be active at a time. Each module contains a separate
pair of 32-byte FIFOs, each of which is dedicated to data flow in a single direction (input or output). The
modules support data transfer to or from the module through either direct or DMA paths. SRAM can be
used as the source or the sink of data, and flash data can be used as source data for IOM transaction.
Command Queue operations are also supported to allow commands to be placed in memory and fetched
and executed in series. The Command Queue interface also includes inter-module flags which allows
event communication between other IOM modules, MSPI modules and external pins through the GPIO
interface.
Also supported in the design are test modes for use in setup and power measurements, and debug
facilities to aid in software/hardware debug.
Bus Interface
CMD Queue
DMA
REGs
INTs
SPI Master Controller
I
2
C Master Controller
FIFO
IO Mux