User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 257 of 909 2019 Ambiq Micro, Inc.
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7.10.2.33CQENDIDX Register
Command Queue End Index
OFFSET: 0x000002C4
INSTANCE 0 ADDRESS: 0x500142C4
Command Queue End Index
Table 391: CQCURIDX Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
RESERVED.
7:0 CQCURIDX 0x0 RW
Can be used to indicate the current position of the command queue by hav-
ing CQ operations write this field. A CQ hardware status flag indicates
when CURIDX and ENDIDX are not equal, allowing SW to pause the CQ
processing until the end index is updated.
Table 392: CQENDIDX Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD CQENDIDX
Table 393: CQENDIDX Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
RESERVED.
7:0 CQENDIDX 0x0 RW
Can be used to indicate the end position of the command queue. A CQ
hardware status bit indices when CURIDX != ENDIDX so that the CQ can
be paused when it reaches the end pointer.