User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 255 of 909 2019 Ambiq Micro, Inc.
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7.10.2.31CQPAUSE Register
Command Queue Pause Mask Register
OFFSET: 0x000002B8
INSTANCE 0 ADDRESS: 0x500142B8
Command Queue Pause Mask Register
Table 387: CQSETCLEAR Register Bits
Bit Name Reset RW Description
31:24 RSVD 0x0 RO
Reserved
23:16 CQFCLR 0x0 WO
Clear CQFlag status bits.
15:8 CQFTOGGLE 0x0 RO
Toggle CQFlag status bits
7:0 CQFSET 0x0 WO
Set CQFlag status bits. Set has priority over clear if both are high.
Table 388: CQPAUSE Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD CQMASK
Table 389: CQPAUSE Register Bits
Bit Name Reset RW Description
31:16 RSVD 0x0 RO
Reserved