User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 252 of 909 2019 Ambiq Micro, Inc.
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7.10.2.28CQSTAT Register
Command Queue Status Register
OFFSET: 0x000002AC
INSTANCE 0 ADDRESS: 0x500142AC
Command Queue Status Register
Table 380: CQADDR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD CQADDR
Table 381: CQADDR Register Bits
Bit Name Reset RW Description
31:29 RSVD 0x0 RO
Reserved
28:0 CQADDR 0x0 RW
Address of command queue buffer in SRAM or flash. The buffer address
must be aligned to a word boundary.
Table 382: CQSTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CQPAUSED
CQERR
CQCPL
CQTIP
Table 383: CQSTAT Register Bits
Bit Name Reset RW Description
31:4 RSVD 0x0 RO
RESERVED.
3 CQPAUSED 0x0 RO
Command queue is currently paused status.
2CQERR 0x0RW
Command queue processing Error. This active high bit signals that an error
was encountered during the CQ operation.
1CQCPL 0x0RW
Command queue operation Complete. This signals the end of the command
queue operation.