User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 251 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
7.10.2.27CQADDR Register
CQ Target Read Address Register
OFFSET: 0x000002A8
INSTANCE 0 ADDRESS: 0x500142A8
Location of the command queue in SRAM or flash memory. This register will increment as CQ operations
commence. Software should only write CQADDR when CQEN is disabled, however the command queue
script itself may update CQADDR in order to perform queue management functions (like resetting the
pointers)
Table 378: CQCFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CQAUTOCLEARMASK
CQPWROFF
CQPRI
CQEN
Table 379: CQCFG Register Bits
Bit Name Reset RW Description
31:4 RSVD 0x0 RO
RESERVED.
3
CQAUTO-
CLEARMASK
0x0 RW
Eanble clear of CQMASK after each pause operation. This may be useful
when using software flags to pause CQ.
2 CQPWROFF 0x0 RW
Power off MSPI domain upon completion of DMA operation.
1CQPRI 0x0RW
Sets the Priority of the command queue dma request
LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
0CQEN 0x0RW
Command queue enable. When set, will enable the processing of the com-
mand queue
DIS = 0x0 - Disable CQ Function
EN = 0x1 - Enable CQ Function