User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 250 of 909 2019 Ambiq Micro, Inc.
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7.10.2.25DMATHRESH Register
DMA Transmit Trigger Threshhold
OFFSET: 0x00000278
INSTANCE 0 ADDRESS: 0x50014278
Indicates FIFO level at which a DMA should be triggered. For most configurations, a setting of 8 is
recommended for both read and write operations.
7.10.2.26CQCFG Register
Command Queue Configuration Register
OFFSET: 0x000002A0
INSTANCE 0 ADDRESS: 0x500142A0
This register controls Command Queueing (CQ) operations in a manner similar to the DMACFG register.
Table 375: DMABCOUNT Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
Reserved
7:0 BCOUNT 0x0 RW
Burst transfer size in bytes. This is the number of bytes transferred when a
FIFO trigger event occurs. Recommended values are 16 or 32.
Table 376: DMATHRESH Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DMATHRESH
Table 377: DMATHRESH Register Bits
Bit Name Reset RW Description
31:4 RSVD 0x0 RO
RESERVED
3:0 DMATHRESH 0x8 RW
DMA transfer FIFO level trigger. For read operations, DMA is triggered
when the FIFO level is greater than this value. For write operations, DMA is
triggered when the FIFO level is less than this level. Each DMA operation
will consist of BCOUNT bytes.