User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 248 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
7.10.2.21DMATARGADDR Register
DMA Target Address Register
OFFSET: 0x00000258
INSTANCE 0 ADDRESS: 0x50014258
DMA Target Address Register
7.10.2.22DMADEVADDR Register
DMA Device Address Register
OFFSET: 0x0000025C
INSTANCE 0 ADDRESS: 0x5001425C
DMA Device Address Register
0DMATIP 0x0RO
DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is
active. The DMA transfer may be waiting on data, transferring data, or wait-
ing for priority. All of these will be indicated with a 1. A 0 will indicate that
the DMA is fully complete and no further transactions will be done.
Table 368: DMATARGADDR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
TARGADDR
Table 369: DMATARGADDR Register Bits
Bit Name Reset RW Description
31:0 TARGADDR 0x0 RW
Target byte address for source of DMA (either read or write). In cases of
non-word aligned addresses, the DMA logic will take care for ensuring only
the target bytes are read/written.
Table 370: DMADEVADDR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DEVADDR
Table 367: DMASTAT Register Bits
Bit Name Reset RW Description