User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 247 of 909 2019 Ambiq Micro, Inc.
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7.10.2.20DMASTAT Register
DMA Status Register
OFFSET: 0x00000254
INSTANCE 0 ADDRESS: 0x50014254
DMA Status Register
4:3 DMAPRI 0x0 RW
Sets the Priority of the DMA request
LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
AUTO = 0x2 - Auto Priority (priority raised once TX FIFO empties or RX
FIFO fills)
2DMADIR 0x0RW
Direction
P2M = 0x0 - Peripheral to Memory (SRAM) transaction
M2P = 0x1 - Memory to Peripheral transaction
1:0 DMAEN 0x0 RW
DMA Enable. Setting this bit to EN will start the DMA operation
DIS = 0x0 - Disable DMA Function
EN = 0x3 - Enable HW controlled DMA Function to manage DMA to flash
devices. HW will automatically handle issuance of instruction/address bytes
based on settings in the FLASH register.
Table 366: DMASTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
SCRERR
DMAERR
DMACPL
DMATIP
Table 367: DMASTAT Register Bits
Bit Name Reset RW Description
31:4 RSVD 0x0 RO
RESERVED.
3SCRERR 0x0RW
Scrambling Access Alignment Error. This active high bit signals that a
scrambling operation was specified for a non-word aligned DEVADDR.
2 DMAERR 0x0 RW
DMA Error. This active high bit signals that an error was encountered during
the DMA operation.
1DMACPL 0x0RW
DMA Transfer Complete. This signals the end of the DMA operation.
Table 365: DMACFG Register Bits
Bit Name Reset RW Description