User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 246 of 909 2019 Ambiq Micro, Inc.
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7.10.2.19DMACFG Register
DMA Configuration Register
OFFSET: 0x00000250
INSTANCE 0 ADDRESS: 0x50014250
DMA Configuration Register
5RXF 0x0RW
Receive FIFO full
4RXO 0x0RW
Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will
stall)
3RXU 0x0RW
Receive FIFO underflow (only occurs when SW reads from an empty FIFO)
2TXO 0x0RW
Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).
1TXE 0x0RW
Transmit FIFO empty.
0CMDCMP 0x0RW
Transfer complete. Note that DMA and CQ operations are layered, so
CMDCMP, DCMP, and CQ* can all be signalled simultaneously
Table 364: DMACFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DMAPWROFF
RSVD
DMAPRI
DMADIR
DMAEN
Table 365: DMACFG Register Bits
Bit Name Reset RW Description
31:19 RSVD 0x0 RO
RESERVED.
18 DMAPWROFF 0x0 RW
Power off MSPI domain upon completion of DMA operation.
17:5 RSVD 0x0 RO
RESERVED.
Table 363: INTSET Register Bits
Bit Name Reset RW Description