User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 245 of 909 2019 Ambiq Micro, Inc.
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7.10.2.18INTSET Register
MSPI Master Interrupts: Set
OFFSET: 0x0000020C
INSTANCE 0 ADDRESS: 0x5001420C
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for
testing purposes).
1TXE 0x0RW
Transmit FIFO empty.
0CMDCMP 0x0RW
Transfer complete. Note that DMA and CQ operations are layered, so
CMDCMP, DCMP, and CQ* can all be signalled simultaneously
Table 362: INTSET Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
SCRERR
CQERR
CQPAUSED
CQUPD
CQCMP
DERR
DCMP
RXF
RXO
RXU
TXO
TXE
CMDCMP
Table 363: INTSET Register Bits
Bit Name Reset RW Description
31:13 RSVD 0x0 RO
RESERVED
12 SCRERR 0x0 RW
Scrambling Alignment Error. Scrambling operations must be aligned to
word (4-byte) start address.
11 CQERR 0x0 RW
Command Queue Error Interrupt
10 CQPAUSED 0x0 RW
Command Queue is Paused.
9CQUPD 0x0RW
Command Queue Update Interrupt. Issued whenever the CQ performs an
operation where address bit[0] is set. Useful for triggering CURIDX inter-
rupts.
8CQCMP 0x0RW
Command Queue Complete Interrupt
7DERR 0x0RW
DMA Error Interrupt
6 DCMP 0x0 RW
DMA Complete Interrupt
Table 361: INTCLR Register Bits
Bit Name Reset RW Description