User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 242 of 909 2019 Ambiq Micro, Inc.
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7.10.2.16INTSTAT Register
MSPI Master Interrupts: Status
OFFSET: 0x00000204
INSTANCE 0 ADDRESS: 0x50014204
Read bits from this register to discover the cause of a recent interrupt.
Table 357: INTEN Register Bits
Bit Name Reset RW Description
31:13 RSVD 0x0 RO
RESERVED
12 SCRERR 0x0 RW
Scrambling Alignment Error. Scrambling operations must be aligned to
word (4-byte) start address.
11 CQERR 0x0 RW
Command Queue Error Interrupt
10 CQPAUSED 0x0 RW
Command Queue is Paused.
9CQUPD 0x0RW
Command Queue Update Interrupt. Issued whenever the CQ performs an
operation where address bit[0] is set. Useful for triggering CURIDX inter-
rupts.
8CQCMP 0x0RW
Command Queue Complete Interrupt
7DERR 0x0RW
DMA Error Interrupt
6 DCMP 0x0 RW
DMA Complete Interrupt
5RXF 0x0RW
Receive FIFO full
4RXO 0x0RW
Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will
stall)
3RXU 0x0RW
Receive FIFO underflow (only occurs when SW reads from an empty FIFO)
2TXO 0x0RW
Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).
1TXE 0x0RW
Transmit FIFO empty.
0CMDCMP 0x0RW
Transfer complete. Note that DMA and CQ operations are layered, so
CMDCMP, DCMP, and CQ* can all be signalled simultaneously