User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 241 of 909 2019 Ambiq Micro, Inc.
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7.10.2.15INTEN Register
MSPI Master Interrupts: Enable
OFFSET: 0x00000200
INSTANCE 0 ADDRESS: 0x50014200
Set bits in this register to allow this module to generate the corresponding interrupt.
Table 354: SCRAMBLING Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SCRENABLE
RSVD SCREND RSVD SCRSTART
Table 355: SCRAMBLING Register Bits
Bit Name Reset RW Description
31 SCRENABLE 0x0 RW
Enables Data Scrambling Region. When 1 reads and writes to the range
will be scrambled. When 0, data will be read/written unmodified. Address
range is specified in 64K granularity and the START/END ranges are
included within the range.
30:26 RSVD 0x0 RO
RESERVED
25:16 SCREND 0x0 RW
Scrambling region end address [25:16] (64K block granularity). The END
block is the LAST block included in the scrambled address range.
15:10 RSVD 0x0 RO
RESERVED
9:0 SCRSTART 0x0 RW
Scrambling region start address [25:16] (64K block granularity). The
START block is the FIRST block included in the scrambled address range.
Table 356: INTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
SCRERR
CQERR
CQPAUSED
CQUPD
CQCMP
DERR
DCMP
RXF
RXO
RXU
TXO
TXE
CMDCMP