User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 240 of 909 2019 Ambiq Micro, Inc.
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7.10.2.14SCRAMBLING Register
External Flash Scrambling Controls
OFFSET: 0x00000120
INSTANCE 0 ADDRESS: 0x50014120
Enables data scrambling for the specified range external flash addresses. Scrambling does not impact
flash access performance.
15:11 RSVD 0x0 RO
RESERVED
10:8 XIPMIXED 0x0 RW
Reserved. Set to 0x0
7XIPSENDI 0x0RW
Indicates whether XIP/AUTO DMA operations should send an instruction
(see READINSTR field and ISIZE field in CFG)
6 XIPSENDA 0x0 RW
Indicates whether XIP/AUTO DMA operations should send an an address
phase (see DMADEVADDR register and ASIZE field in CFG)
5 XIPENTURN 0x0 RW
Indicates whether XIP/AUTO DMA operations should enable TX->RX turn-
around cycles
4 XIPBIGENDIAN 0x0 RW
Indicates whether XIP/AUTO DMA data transfers are in big or little endian
format
3:2 XIPACK 0x0 RW
Controls transmission of Micron XIP acknowledge cycles (Micron Flash
devices only)
NOACK = 0x0 - No acknowledege sent. Data IOs are tristated the first turn-
around cycle
ACK = 0x2 - Positive acknowledege sent. Data IOs are driven to 0 the first
turnaround cycle to acknowledge XIP mode
TERMINATE = 0x3 - Negative acknowledege sent. Data IOs are driven to 1
the first turnaround cycle to terminate XIP mode. XIPSENDI should be
reenabled for the next transfer
1 RSVD 0x0 RO
RESERVED
0 XIPEN 0x0 RW
Enable the XIP (eXecute In Place) function which effectively enables the
address decoding of the MSPI device in the flash/cache address space at
address 0x04000000-0x07FFFFFF.
Table 353: FLASH Register Bits
Bit Name Reset RW Description