User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 236 of 909 2019 Ambiq Micro, Inc.
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7.10.2.10MSPICFG Register
MSPI Module Configuration
OFFSET: 0x00000100
INSTANCE 0 ADDRESS: 0x50014100
Timing configuration bits for the MSPI module. PRSTN, IPRSTN, and FIFORESET can be used to reset
portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency
and TX/RX capture timings.
7:5 RSVD 0x0 RO
RESERVED
4:0 TXTHRESH 0x0 RW
Number of entries in TX FIFO that cause TXF interrupt
Table 346: MSPICFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
PRSTN
IPRSTN
FIFORESET
RSVD CLKDIV
RSVD
IOMSEL
TXNEG
RXNEG
RXCAP
APBCLK
Table 347: MSPICFG Register Bits
Bit Name Reset RW Description
31 PRSTN 0x1 RW
Peripheral reset. Master reset to the entire MSPI module (DMA, XIP, and
transfer state machines). 1=normal operation, 0=in reset.
30 IPRSTN 0x1 RW
IP block reset. Write to 0 to put the transfer module in reset or 1 for normal
operation. This may be required after error conditions to clear the transfer
on the bus.
29 FIFORESET 0x0 RW
Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal operation. May
be used to manually flush the FIFO in error handling.
28:14 RSVD 0x0 RO
RESERVED
Table 345: THRESHOLD Register Bits
Bit Name Reset RW Description