User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 229 of 909 2019 Ambiq Micro, Inc.
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7.10.1 Register Memory Map
Table 327: MSPI Register Map
Address(s) Register Name Description
0x50014000 CTRL MSPI PIO Transfer Control/Status Register
0x50014004 CFG MSPI Transfer Configuration Register
0x50014008 ADDR MSPI Transfer Address Register
0x5001400C INSTR MSPI Transfer Instruction
0x50014010 TXFIFO TX Data FIFO
0x50014014 RXFIFO RX Data FIFO
0x50014018 TXENTRIES TX FIFO Entries
0x5001401C RXENTRIES RX FIFO Entries
0x50014020 THRESHOLD TX/RX FIFO Threshhold Levels
0x50014100 MSPICFG MSPI Module Configuration
0x50014104 PADCFG MSPI Output Pad Configuration
0x50014108 PADOUTEN MSPI Output Enable Pad Configuration
0x5001410C FLASH
Configuration for XIP/DMA support of SPI flash
modules.
0x50014120 SCRAMBLING External Flash Scrambling Controls
0x50014200 INTEN MSPI Master Interrupts: Enable
0x50014204 INTSTAT MSPI Master Interrupts: Status
0x50014208 INTCLR MSPI Master Interrupts: Clear
0x5001420C INTSET MSPI Master Interrupts: Set
0x50014250 DMACFG DMA Configuration Register
0x50014254 DMASTAT DMA Status Register
0x50014258 DMATARGADDR DMA Target Address Register
0x5001425C DMADEVADDR DMA Device Address Register
0x50014260 DMATOTCOUNT DMA Total Transfer Count
0x50014264 DMABCOUNT DMA BYTE Transfer Count
0x50014278 DMATHRESH DMA Transmit Trigger Threshhold
0x500142A0 CQCFG Command Queue Configuration Register
0x500142A8 CQADDR CQ Target Read Address Register
0x500142AC CQSTAT Command Queue Status Register
0x500142B0 CQFLAGS Command Queue Flag Register
0x500142B4 CQSETCLEAR Command Queue Flag Set/Clear Register
0x500142B8 CQPAUSE Command Queue Pause Mask Register
0x500142C0 CQCURIDX Command Queue Current Index
0x500142C4 CQENDIDX Command Queue End Index