User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 224 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
The soft flags can be set/cleared/toggled via writes to the CQSETCLEAR register and their status can be
read by software by reading the CQFLAGS register directly. The CQPAUSE mask bits are enumerated in
the same manner.
In order to minimize the need to pause for individual operations, the CQ will automatically pause any time
the MSPI's transfer block is active (for PIO, DMA, or XIP operations). Thus, whenever the CQ enables a
DMA operation, there is an implicit pause until the operation completes, and then the CQ will resume
fetching additional commands. To terminate the CQ processing, the CQ or software should set the top-
most CQPAUSE bit (STOP), which will cause the MSPI to terminate processing of the command queue
and issue a CQCPL interrupt.
7.6.4 Using the CQ Index registers
The MSPI command queuing implementation also includes a pair of registers that allow software to
manage a list of outstanding operations: CQCURIDX and CQENDIDX. When initializing the command
queue software can set both of these registers to the same value, which indicate an index or reference into
the position of the command queue. The CQPAUSE can then be set to CQIDX and the command queue
enabled. Since the CQCURIDX equals the CQENDIDX, the command queue will immediately pause and
wait for them to be
For each group of commands in the command queue, software can place a write to the CQCURIDX after
each DMA operation in the command queue and then directly write the CQENDIDX register with the index
of the last operation in the queue. Since the CQENDIDX now mismatches the CQCURIDX, the command
queue will begin processing commands and start working its way through the queue. After completing the
first operation, the command queue will include a write to the CQCURIDX to indicate that the operation has
completed, and the CQ logic will check to see if the CQCURIDX equals the CQENDIDX and either pause
or continue processing until the two are equal again.
This mechanism allows software to asynchronously post additional operations to the command queue by
simply writing the new commands to memory and then updating the CQENDIDX to the index of the last
operation. Because the MSPI CQ hardware simply looks for a match between the registers, software may
roll over from 0xFF to 0x00 or use the indices in any manner they see fit as long as the end index value is
not found elsewhere in the command queue.
Software can monitor the progress of the MSPI's CQ processing by enabling the DMACPL interrupt, which
will generate an interrupt after each DMA completion. The interrupt routine can read the CQCURIDX
register to determine which operations have completed in order to return the proper status to the
application.
5 Soft SWFLAG5 Software flag
4 Soft SWFLAG4 Software flag
3 Soft SWFLAG3 Software flag
2 Soft SWFLAG2 Software flag
1 Soft IOM1START
Flag wired to IOM devices as a hard flag for
intercommunication. Typically indicates that
buffer 1 has been filled by MSPI and can be
emptied by the IOM.
0 Soft IOM0START
Flag wired to IOM devices as a hard flag for
intercommunication. Typically indicates that
buffer 0 has been filled by MSPI and can be
emptied by the IOM.
Table 324: CQFLAGS
Bit Type Mnemonic Description/Use