User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 222 of 909 2019 Ambiq Micro, Inc.
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The AM_REG macros can be used to construct the CQ table in a manner similar to below:
uint32_t *cqptr = 0x10000;
*cqptr++ = AM_REG_ADDR(MSPI,DMADEVADDR);
*cqptr++ = devaddr; // set device address (for encryption)
*cqptr++ = AM_REG_ADDR(MSPI,DMATARGADDR);
*cqptr++ = data_buffer; // set source address in memory
*cqptr++ = AM_REG_ADDR(MSPI,DMATOTCOUNT);
*cqptr++ = 4*num_words; // set total number of bytes
*cqptr++ = AM_REG_ADDR(MSPI,DMACFG);
*cqptr++ = AM_REG_MSPI_DMACFG_DMAEN_AUTO |
AM_REG_MSPI_DMACFG_DMADIR_M2P); // enable DMA write
*cqptr++ = AM_REG_ADDR(MSPI,CQPAUSE);
*cqptr++ = AM_REG_MSPI_CQFLAGS_STOP_M;
7.6.2 CQ Interrupts
The MSPI CQ module provides several interrupts to provide feedback to software as the MSPI works
through its command queue.
▪ CQERR: Indicates that the command queue encountered an error when fetching the command queue
instructions. This can be caused by an invalid CQ pointer that points to an invalid flash or SRAM address
(SRAM powered down, etc).
▪ CQPAUSED: Indicates that the command queue has encountered a pause condition. This can be trig-
gered by an index match or when the CQ is waiting on a software or hardware flag.
▪ CQCMP: Indicates that the command queue has completed operations. This is typically used when the
command queue is executing a single-shot set of commands which end with the CQ writing the STOP bit
in the CQPAUSE register.
▪ CQUPD: Indicates a generic CQ update interrupt which is triggered by execution of a command queue
entry.
Software can generate a CQUPD interrupt at any point during command queue operation by setting bit[0]
of the register address of the command to a 1 (basically OR 0x1 with the address portion of a CQ entry.
Table 323: Command Queue Example
Address Data Description
0x10000 0x50014258 DMATARGADDR register address
0x10004 0x00002800
Data to write to DMATARGADDR (i.e. 0x2800
is the target buffer)
0x10008 0x5001425C DMADEVADDR register address
0x1000C 0x00304000 Address within flash device
0x10010 0x50014260 DMATOTCOUNT register address
0x10014 0x00000100 Transfer 256 bytes of data
0x10018 0x50014250 DMACFG register address
0x1001C 0x00000003
AUTO DMA enable on peripheral to memory
transfer
0x10020 0x50014288 CQPAUSE register address
0x10024 0x00008000 End of Command Queue (write to STOP bit)