User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 219 of 909 2019 Ambiq Micro, Inc.
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7.4 DMA Operations
The MSPI controller tightly integrates the DMA controller with the transfer interface and automatically
handles sequencing of instructions and address to serial flash device and the subsequent transfer of data
to/from system memory. Before starting DMA operations, software should have already configured the
CFG register (to specify device configuration) and the FLASH register (to specify the template used for
DMA operations). Software should first set up the static DMA parameters which specify the DMA burst
parameters:
AM_REG(MSPI,DMATHRESH)=8; // Issue new DMA at FIFO half empty/full condition
AM_REG(MSPI,DMABCOUNT)=32; // burst count=32 bytes (8 words)
The MSPI implements a single FIFO for both TX and RX transfers as well as a single threshold value for
RX/TX operations. In most cases, the DMATHRESH should be set at 8 to indicate that a TX DMA (read
from SRAM) will be triggered when the FIFO drops below eight entries and will trigger an RX DMA (write to
SRAM) when the FIFO level reaches eight entries. The BCOUNT indicates the number of words that will
be transferred each time that DMA is triggered. The DMA will also trigger automatically to flush or fill the
FIFOs at the end of transfer if the total count is not a multiple of 32 bytes.
To initiate a DMA transfer, software should issue the following register operations:
AM_REG(MSPI,DMADEVADDR)=(uint32_t) addr; // set device address
AM_REG(MSPI,DMATARGADDR)=(uint32_t) data; // set address in system memory
AM_REG(MSPI,DMATOTCOUNT)=(count<<2); // set total number of bytes
AM_REG(MSPI,DMACFG)=AM_REG_MSPI_DMACFG_DMAEN | // enable DMA
AM_REG_MSPI_DMACFG_DMADIR_P2M; // peripheral to memory
When complete, the MSPI will issue the DMACPL interrupt and software can monitor the status by reading
the DMATIP bit in the DMASTAT register. Transfers to the flash device are initiated by setting the DMADIR
field to M2P (Memory to Peripheral).
The controller will use the template in the FLASH register to determine whether to send the instruction and
address phases (XIPSENDI, XIPSENDA) and whether to insert turnaround cycles (XIPENTURN).
Instruction and address lengths are determined by the settings in the CFG register and the address and
transfer count are set by the DMADEVADDR and DMATOTCOUNT registers. The instruction send for
read (RX) operations is specified in the READINSTR field of the FLASH register and likewise the
WRITEINSTR field is used when transmitting data to the flash device.
If the AUTO DMA cannot be used because the device's characteristics don't fit into the template, software
can issue PIO operations to initiate a more complex transfer setup and then enable DMA for just the bulk
DMA portions using the DMAEN_EN instead of DMAEN_AUTO.
Optionally, the MSPI can turn off it's power domain at the end of a DMA transfer if the DMAPWROFF bit is
set in the DMACFG register. The domain will only power off once the entire DMA is complete (i.e. writes
have been committed to system memory or have completed to the external flash device).