User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 215 of 909 2019 Ambiq Micro, Inc.
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6.3.2.36 BLEDBG Register
BLEIF Master Debug Register
OFFSET: 0x00000410
INSTANCE 0 ADDRESS: 0x5000C410
Debug control
2:0 B2MSTATE 0x0 RO
State of the BLE Core logic.
RESET = 0x0 - Reset State
Shutdown = 0x0 - Shutdown state
Sleep = 0x1 - Sleep state.
Standby = 0x2 - Standby State
Idle = 0x3 - Idle state
Active = 0x4 - Active state.
Table 321: BLEDBG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DBGDATA
APBCLKON
IOCLKON
DBGEN
Table 322: BLEDBG Register Bits
Bit Name Reset RW Description
31:3 DBGDATA 0x0 RW
Debug data
2 APBCLKON 0x0 RW
APBCLK debug clock control. Enable APB_CLK to be active when this bit is
'1'. Otherwise, the clock is controlled with gating from the logic as needed.
1 IOCLKON 0x0 RW
IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'.
Otherwise, the clock is controlled with gating from the logic as needed.
0 DBGEN 0x0 RW
Debug Enable. Setting this bit will enable the update of data within this reg-
ister, otherwise it is clock gated for power savings
Table 320: BSTATUS Register Bits
Bit Name Reset RW Description