User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 214 of 909 2019 Ambiq Micro, Inc.
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Table 319: BSTATUS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BLEHREQ
BLEHACK
PWRST
BLEIRQ
WAKEUP
DCDCFLAG
DCDCREQ
SPISTATUS
B2MSTATE
Table 320: BSTATUS Register Bits
Bit Name Reset RW Description
31:13 RSVD 0x0 RO
RESERVED
12 BLEHREQ 0x0 RO
Value of the BLEHREQ signal to the power control unit. The BLEHREQ sig-
nal is sent from the BLEIF module to the power control module to request
the BLEH power up. When the BLEHACK signal is asserted,
11 BLEHACK 0x0 RO
Value of the BLEHACK signal from the power control unit. If the signal is '1',
the BLEH power is active and ready for use.
10:8 PWRST 0x0 RO
Current status of the power state machine
OFF = 0x0 - Internal power state machine is disabled and will not sequence
the BLEH power domain. The values of the overrides will be used to drive
the output sequencing signals
INIT = 0x1 - Initialization state. BLEH not powered
PWRON = 0x2 - Waiting for the power-up of the BLEH
ACTIVE = 0x3 - The BLE Core is powered and active
SLEEP = 0x6 - The BLE Core has entered sleep mode and the power
request is inactive
SHUTDOWN = 0x4 - The BLE Core is in shutdown mode
7BLEIRQ 0x0RO
Status of the BLEIRQ signal from the BLE Core. A value of 1 indicates that
read data is available in the core and a read operation needs to be per-
formed.
6 WAKEUP 0x0 RO
Value of the WAKEUP signal to the BLE Core. The WAKEUP signals is sent
from the BLEIF to the BLECORE to request the BLE Core transition from
sleep state to active state.
5 DCDCFLAG 0x0 RO
Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a sig-
nal to the BLE Core indicating that the BLEH power is active.
4 DCDCREQ 0x0 RO
Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is
sent from the core to the BLEIF module when the BLE core requires BLEH
power to be active. When activated, this is
3 SPISTATUS 0x0 RO
Value of the SPISTATUS signal from the BLE Core. The signal is asserted
when the BLE Core is able to accept write data via the SPI interface. Data
should be transmitted to the