User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 213 of 909 2019 Ambiq Micro, Inc.
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6.3.2.34 PWRCMD Register
BLE Power command interface
OFFSET: 0x00000308
INSTANCE 0 ADDRESS: 0x5000C308
Sends power related commands to the power state machine in the BLE IF module.
6.3.2.35 BSTATUS Register
BLE Core status
OFFSET: 0x0000030C
INSTANCE 0 ADDRESS: 0x5000C30C
Status of the BLE Core interface signals
0 PWRSMEN 0x0 RW
Enable the power state machine for automatic sequencing and control of
power states of the BLE Core module.
ON = 0x1 - Internal power state machine is enabled and will sequence the
BLEH power domain as indicated in the design document. Overrides for the
power signals are not enabled.
OFF = 0x0 - Internal power state machine is disabled and will not sequence
the BLEH power domain. The values of the overrides will be used to drive
the output sequencing signals
Table 317: PWRCMD Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
RESTART
WAKEREQ
Table 318: PWRCMD Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
Reserved
1 RESTART 0x0 WO
Restart the BLE Core after going into the shutdown state. Only valid when in
the shutdown state.
0 WAKEREQ 0x0 WO
Wake request from the MCU. When asserted (1), the BLE Interface logic will
assert the wakeup request signal to the BLE Core. Only recognized when in
the sleep state
Table 316: BLECFG Register Bits
Bit Name Reset RW Description