User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 212 of 909 2019 Ambiq Micro, Inc.
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15:14 SPIISOCTL 0x0 RW
Configuration of BLEH isolation controls for SPI related signals.
ON = 0x3 - SPI signals from BLE Core to/from MCU Core are isolated.
OFF = 0x2 - SPI signals from BLE Core to/from MCU Core are not isolated.
AUTO = 0x0 - SPI signals from BLE Core to/from MCU Core are automati-
cally isolated by the logic
13:12 PWRISOCTL 0x0 RW
Configuration of BLEH isolation control for power related signals.
ON = 0x3 - BLEH power signal isolation to on (isolated).
OFF = 0x2 - BLEH power signal isolation to off (not isolated).
AUTO = 0x0 - BLEH Power signal isolation is controlled automatically
through the interface logic
11 STAYASLEEP 0x0 RW
Set to prevent the BLE power control module from waking up the BLE Core
after going into power down. To be used for graceful shutdown, set by soft-
ware prior to powering off and will allow assertion of reset from sleep state.
10 FRCCLK 0x0 RW
Force the clock in the BLEIF to be always running
9MCUFRCSLP 0x0 RW
Force power state machine to go to the sleep state. Intended for debug only.
Has no effect on the actual BLE Core state, only the state of the BLEIF inter-
face state machine.
8 WT4ACTOFF 0x0 RW
Debug control of BLEIF power state machine. Allows transition into the
active state in the BLEIF state without waiting for dcdc req from BLE Core.
7:6 BLEHREQCTL 0x0 RW
BLEH power on request override. The value of this field will be sent to the
BLE Core when the PWRSM is off. Otherwise, the value is supplied from
internal logic.
ON = 0x3 - BLEH Power-on reg signal is set to on (1).
OFF = 0x2 - BLEH Power-on signal is set to off (0).
AUTO = 0x0 - BLEH Power-on signal is controlled by the PWRSM logic and
automatically controlled
5:4 DCDCFLGCTL 0x0 RW
DCDCFLG signal override. The value of this field will be sent to the BLE
Core when the PWRSM is off. Otherwise, the value is supplied from internal
logic.
ON = 0x3 - DCDC Flag signal is set to on (1).
OFF = 0x2 - DCDC Flag signal is set to off (0).
AUTO = 0x0 - DCDC Flag signal is controlled by the PWRSM logic and
automatically controlled
3:2 WAKEUPCTL 0x0 RW
WAKE signal override. Controls the source of the WAKE signal to the BLE
Core.
ON = 0x3 - Wake signal is set to on (1).
OFF = 0x2 - Wake signal is set to off (0).
AUTO = 0x0 - Wake signal is controlled by the PWRSM logic and automati-
cally controlled
1 BLERSTN 0x0 RW
Reset line to the BLE Core. This will reset the BLE core when asserted ('0')
and must be written to '1' prior to performing any BTLE related operations to
the core.
ACTIVE = 0x1 - The reset signal is active (0)
INACTIVE = 0x0 - The reset signal is inactive (1)
Table 316: BLECFG Register Bits
Bit Name Reset RW Description