User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 210 of 909 2019 Ambiq Micro, Inc.
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INSTANCE 0 ADDRESS: 0x5000C300
Controls the configuration of the SPI master module, including POL/PHA, LSB, flow control, and delays for
MISO and MOSI
Table 313: MSPICFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
MSPIRST
DOUTDLY
DINDLY
SPILSB
RDFCPOL
WTF-
RSVD
RDFC
WTFC
RSVD
FULLDUP
SPHA
SPOL
Table 314: MSPICFG Register Bits
Bit Name Reset RW Description
31 RSVD 0x0 RO
RESERVED
30 MSPIRST 0x1 RW
Bit is deprecated. setting it will have no effect.
29:27 DOUTDLY 0x0 RW
Delay tap to use for the output signal (MOSI). This give more hold time on
the output data.
26:24 DINDLY 0x0 RW
Delay tap to use for the input signal (MISO). This gives more hold time on
the input data.
23 SPILSB 0x0 RW
Selects data transfer as MSB first (0) or LSB first (1) for the data portion of
the SPI transaction. The offset bytes are always transmitted MSB first.
MSB = 0x0 - Send and receive MSB bit first
LSB = 0x1 - Send and receive LSB bit first
22 RDFCPOL 0x0 RW
Selects the read flow control signal polarity. When set, the clock will be held
low until the flow control is de-asserted.
NORMAL = 0x0 - SPI_STATUS signal from BLE Core high(1) creates flow
control and new read spi transactions will not be started until the signal goes
low.(default)
INVERTED = 0x1 - SPI_STATUS signal from BLE Core low(0) creates flow
control and new read spi transactions will not be started until the signal goes
high.
21 WTFCPOL 0x0 RW
Selects the write flow control signal polarity. The transfers are halted when
the selected flow control signal is OPPOSITE polarity of this bit. (For exam-
ple: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers).
NORMAL = 0x0 - SPI_STATUS signal from BLE Core high(1) creates flow
control and new write spi transactions will not be started until the signal
goes low.(default)
INVERTED = 0x1 - SPI_STATUS signal from BLE Core high(1) creates
low(0) control and new write spi transactions will not be started until the sig-
nal goes high.
20:18 RSVD 0x0 R0
Reserved