User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 203 of 909 2019 Ambiq Micro, Inc.
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6.3.2.23 CQCFG Register
Command Queue Configuration Register
OFFSET: 0x00000248
INSTANCE 0 ADDRESS: 0x5000C248
Controls parameters and options for execution of the command queue operation. To enable command
queue, create this in memory, set the address, and enable it with a write to CQEN
Table 294: DMASTAT Register Bits
Bit Name Reset RW Description
31:3 RSVD 0x0 RO
RESERVED.
2 DMAERR 0x0 RW
DMA Error. This active high bit signals that an error was encountered during
the DMA operation.
1DMACPL 0x0RW
DMA Transfer Complete. This signals the end of the DMA operation. This bit
can be cleared by writing to 0.
0DMATIP 0x0RO
DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is
active. The DMA transfer may be waiting on data, transferring data, or wait-
ing for priority.
Table 295: CQCFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CQPRI
CQEN
Table 296: CQCFG Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
RESERVED.
1CQPRI 0x0RW
Sets the Priority of the command queue dma request.
LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
0CQEN 0x0RW
Command queue enable. When set, will enable the processing of the com-
mand queue and fetches of address/data pairs will proceed from the word
address within the CQADDR register. Can be disabled
DIS = 0x0 - Disable CQ Function
EN = 0x1 - Enable CQ Function