User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 201 of 909 2019 Ambiq Micro, Inc.
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6.3.2.20 DMATOTCOUNT Register
DMA Total Transfer Count
OFFSET: 0x0000023C
INSTANCE 0 ADDRESS: 0x5000C23C
Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as
the data is transferred, and will be 0 at the completion of the DMA operation.
6.3.2.21 DMATARGADDR Register
DMA Target Address Register
OFFSET: 0x00000240
INSTANCE 0 ADDRESS: 0x5000C240
7:2 RSVD 0x0 RO
RESERVED.
1DMADIR 0x0RW
Direction
P2M = 0x0 - Peripheral to Memory (SRAM) transaction. To be set when
doing IOM read operations, i.e., reading data from external devices.
M2P = 0x1 - Memory to Peripheral transaction. To be set when doing IOM
write operations, i.e., writing data to external devices.
0 DMAEN 0x0 RW
DMA Enable. Setting this bit to EN will start the DMA operation. This should
be the last DMA related register set prior to issuing the command
DIS = 0x0 - Disable DMA Function
EN = 0x1 - Enable DMA Function
Table 289: DMATOTCOUNT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSRVDD TOTCOUNT
Table 290: DMATOTCOUNT Register Bits
Bit Name Reset RW Description
31:12 RSRVDD 0x0 RO
Reserved
11:0 TOTCOUNT 0x0 RW
Triggered DMA from Command complete event occurred. Bit is read only
and can be cleared by disabling the DTHR trigger enable or by disabling
DMA.
Table 288: DMACFG Register Bits
Bit Name Reset RW Description