User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 199 of 909 2019 Ambiq Micro, Inc.
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6.3.2.18 DMATRIGSTAT Register
DMA Trigger Status Register
OFFSET: 0x00000234
INSTANCE 0 ADDRESS: 0x5000C234
Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only
and some can be reset via a write of 0.
Table 283: DMATRIGEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DTHREN
DCMDCMPEN
Table 284: DMATRIGEN Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
RESERVED.
1 DTHREN 0x0 RW
Trigger DMA upon THR level reached. For M2P DMA operations (IOM
writes), the trigger will assert when the write FIFO has (WTHR/4) number of
words free in the write FIFO, and will transfer (WTHR/4) number of words
0 DCMDCMPEN 0x0 RW
Trigger DMA upon command complete. Enables the trigger of the DMA
when a command is completed. When this event is triggered, the number of
words transferred will be the lesser of the remaining TOTCOUNT bytes, or
the number of bytes in the FIFO when the command completed. If this is
disabled, and the number of bytes in the FIFO is equal or greater than the
TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure
read data is stored when the DMA is completed.
Table 285: DMATRIGSTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DTOTCMP
DTHR
DCMDCMP