User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 198 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
6.3.2.17 DMATRIGEN Register
DMA Trigger Enable Register
OFFSET: 0x00000230
INSTANCE 0 ADDRESS: 0x5000C230
Provides control on which event will trigger the DMA transfer after the DMA operation is setup and
enabled. The trigger event will cause a number of bytes (depending on trigger event) to be
9 DCMP 0x0 RW
DMA Complete. Processing of the DMA operation has completed and the
DMA submodule is returned into the idle state
8 BLECSSTAT 0x0 RW
BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from
the BLE Core is asserted, indicating that SPI writes can be done to the BLE
Core.
7 BLECIRQ 0x0 RW
BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE
Core is asserted, indicating the availability of read data from the BLE Core.
6ICMD 0x0RW
illegal command interrupt. Asserted when a command is written when an
active command is in progress.
5IACC 0x0RW
illegal FIFO access interrupt. Asserted when there is a overflow or under-
flow event
4 B2MST 0x0 RW
B2M State change interrupt. Asserted on any change in the B2M_STATE
signal from the BLE Core.
3FOVFL 0x0RW
Write FIFO Overflow interrupt. This occurs when software tries to write to a
full fifo. The current operation does not stop.
2 FUNDFL 0x0 RW
Read FIFO Underflow interrupt. Asserted when a pop operation is done to a
empty read FIFO.
1THR 0x0RW
FIFO Threshold interrupt. For write operations, asserted when the number
of free bytes in the write FIFO equals or exceeds the WTHR field.
0CMDCMP 0x0RW
Command Complete interrupt. Asserted when the current operation has
completed. For repeated commands, this will only be asserted when the
final repeated command is completed.
Table 282: INTSET Register Bits
Bit Name Reset RW Description