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Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 196 of 909 2019 Ambiq Micro, Inc.

6.3.2.16 INTSET Register

IO Master Interrupts: Set

OFFSET: 0x0000022C

12 CQUPD 0x0 RW

Command queue write operation executed a register write with the register

address bit 0 set to 1. The low address bits in the CQ address fields are

unused and bit 0 can be used to trigger an interrupt to indicate when this

11 CQPAUSED 0x0 RW

Command queue is paused due to an active event enabled in the PAU-

SEEN register. The interrupt is posted when the event is enabled within the

PAUSEEN register, the mask is active in the CQIRQMASK field and the

event occurs.

10 DERR 0x0 RW

DMA Error encountered during the processing of the DMA command. The

DMA error could occur when the memory access specified in the DMA oper-

ation is not available or incorrectly specified.

9 DCMP 0x0 RW

DMA Complete. Processing of the DMA operation has completed and the

DMA submodule is returned into the idle state

8 BLECSSTAT 0x0 RW

BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from

the BLE Core is asserted, indicating that SPI writes can be done to the BLE

Core.

7 BLECIRQ 0x0 RW

BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE

Core is asserted, indicating the availability of read data from the BLE Core.

6ICMD 0x0RW

illegal command interrupt. Asserted when a command is written when an

active command is in progress.

5IACC 0x0RW

illegal FIFO access interrupt. Asserted when there is a overflow or under-

flow event

4 B2MST 0x0 RW

B2M State change interrupt. Asserted on any change in the B2M_STATE

signal from the BLE Core.

3FOVFL 0x0RW

Write FIFO Overflow interrupt. This occurs when software tries to write to a

full fifo. The current operation does not stop.

2 FUNDFL 0x0 RW

Read FIFO Underflow interrupt. Asserted when a pop operation is done to a

empty read FIFO.

1THR 0x0RW

FIFO Threshold interrupt. For write operations, asserted when the number

of free bytes in the write FIFO equals or exceeds the WTHR field.

0CMDCMP 0x0RW

Command Complete interrupt. Asserted when the current operation has

completed. For repeated commands, this will only be asserted when the

final repeated command is completed.

Table 280: INTCLR Register Bits

Bit Name Reset RW Description