User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 195 of 909 2019 Ambiq Micro, Inc.
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6.3.2.15 INTCLR Register
IO Master Interrupts: Clear
OFFSET: 0x00000228
INSTANCE 0 ADDRESS: 0x5000C228
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
1THR 0x0RW
FIFO Threshold interrupt. For write operations, asserted when the number
of free bytes in the write FIFO equals or exceeds the WTHR field.
0CMDCMP 0x0RW
Command Complete interrupt. Asserted when the current operation has
completed. For repeated commands, this will only be asserted when the
final repeated command is completed.
Table 279: INTCLR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
B2MSHUTDN
B2MACTIVE
B2MSLEEP
CQERR CQUPD
CQPAUSED
DERR
DCMP
BLECSSTAT
BLECIRQ
ICMD
IACC
B2MST
FOVFL
FUNDFL
THR
CMDCMP
Table 280: INTCLR Register Bits
Bit Name Reset RW Description
31:17 RSVD 0x0 RO
RESERVED
16 B2MSHUTDN 0x0 RW
Revision A: The B2M_STATE from the BLE Core transitioned into shutdown
state.
Revision B: Falling BLE Core Status signal. Asserted when the BLE_STA-
TUS signal from the BLE Core is de-asserted (1 -> 0)
15 B2MACTIVE 0x0 RW
Revision A: The B2M_STATE from the BLE Core transitioned into the active
state.
Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ sig-
nal from the BLE Core is de-asserted (1 -> 0)
14 B2MSLEEP 0x0 RW
The B2M_STATE from the BLE Core transitioned into the sleep state
13 CQERR 0x0 RW
Command queue error during processing. When an error occurs, the sys-
tem will stop processing and halt operations to allow software to take recov-
ery actions
Table 278: INTSTAT Register Bits
Bit Name Reset RW Description