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Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 194 of 909 2019 Ambiq Micro, Inc.
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15 B2MACTIVE 0x0 RW
Revision A: The B2M_STATE from the BLE Core transitioned into the active
state.
Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ sig-
nal from the BLE Core is de-asserted (1 -> 0)
14 B2MSLEEP 0x0 RW
The B2M_STATE from the BLE Core transitioned into the sleep state
13 CQERR 0x0 RW
Command queue error during processing. When an error occurs, the sys-
tem will stop processing and halt operations to allow software to take recov-
ery actions
12 CQUPD 0x0 RW
Command queue write operation executed a register write with the register
address bit 0 set to 1. The low address bits in the CQ address fields are
unused and bit 0 can be used to trigger an interrupt to indicate when this
register write is performed by the CQ operation.
11 CQPAUSED 0x0 RW
Command queue is paused due to an active event enabled in the PAU-
SEEN register. The interrupt is posted when the event is enabled within the
PAUSEEN register, the mask is active in the CQIRQMASK field and the
event occurs.
10 DERR 0x0 RW
DMA Error encountered during the processing of the DMA command. The
DMA error could occur when the memory access specified in the DMA oper-
ation is not available or incorrectly specified.
9 DCMP 0x0 RW
DMA Complete. Processing of the DMA operation has completed and the
DMA submodule is returned into the idle state
8 BLECSSTAT 0x0 RW
BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from
the BLE Core is asserted, indicating that SPI writes can be done to the BLE
Core.
7 BLECIRQ 0x0 RW
BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE
Core is asserted, indicating the availability of read data from the BLE Core.
6ICMD 0x0RW
illegal command interrupt. Asserted when a command is written when an
active command is in progress.
5IACC 0x0RW
illegal FIFO access interrupt. Asserted when there is a overflow or under-
flow event
4 B2MST 0x0 RW
B2M State change interrupt. Asserted on any change in the B2M_STATE
signal from the BLE Core.
3FOVFL 0x0RW
Write FIFO Overflow interrupt. This occurs when software tries to write to a
full fifo. The current operation does not stop.
2 FUNDFL 0x0 RW
Read FIFO Underflow interrupt. Asserted when a pop operation is done to a
empty read FIFO.
Table 278: INTSTAT Register Bits
Bit Name Reset RW Description