User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 193 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
6.3.2.14 INTSTAT Register
IO Master Interrupts: Status
OFFSET: 0x00000224
INSTANCE 0 ADDRESS: 0x5000C224
Read bits from this register to discover the cause of a recent interrupt.
4 B2MST 0x0 RW
B2M State change interrupt. Asserted on any change in the B2M_STATE
signal from the BLE Core.
3FOVFL 0x0RW
Write FIFO Overflow interrupt. This occurs when software tries to write to a
full fifo. The current operation does not stop.
2 FUNDFL 0x0 RW
Read FIFO Underflow interrupt. Asserted when a pop operation is done to a
empty read FIFO.
1THR 0x0RW
FIFO Threshold interrupt. For write operations, asserted when the number
of free bytes in the write FIFO equals or exceeds the WTHR field.
0CMDCMP 0x0RW
Command Complete interrupt. Asserted when the current operation has
completed. For repeated commands, this will only be asserted when the
final repeated command is completed.
Table 277: INTSTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
B2MSHUTDN
B2MACTIVE
B2MSLEEP
CQERR CQUPD
CQPAUSED
DERR
DCMP
BLECSSTAT
BLECIRQ
ICMD
IACC
B2MST
FOVFL
FUNDFL
THR
CMDCMP
Table 278: INTSTAT Register Bits
Bit Name Reset RW Description
31:17 RSVD 0x0 RO
RESERVED
16 B2MSHUTDN 0x0 RW
Revision A: The B2M_STATE from the BLE Core transitioned into shutdown
state.
Revision B: Falling BLE Core Status signal. Asserted when the BLE_STA-
TUS signal from the BLE Core is de-asserted (1 -> 0)
Table 276: INTEN Register Bits
Bit Name Reset RW Description