User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 188 of 909 2019 Ambiq Micro, Inc.
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6.3.2.9 CMD Register
Command and offset Register
OFFSET: 0x0000020C
INSTANCE 0 ADDRESS: 0x5000C20C
Writes to this register will start an IO transaction, as well as set various parameters for the command itself.
Reads will return the command value written to the CMD register.
Table 266: CLKCFG Register Bits
Bit Name Reset RW Description
31:13 RSVD 0x0 RO
RESERVED
12 DIV3 0x0 RW
Enable of the divide by 3 of the source IOCLK.
11 CLK32KEN 0x0 RW
Enable for the 32Khz clock to the BLE module
10:8 FSEL 0x0 RW
Select the input clock frequency.
MIN_PWR = 0x0 - Selects the minimum power clock. This setting should be
used whenever the IOM is not active.
HFRC = 0x1 - Selects the HFRC as the input clock.
HFRC_DIV2 = 0x2 - Selects the HFRC / 2 as the input clock.
HFRC_DIV4 = 0x3 - Selects the HFRC / 4 as the input clock.
HFRC_DIV8 = 0x4 - Selects the HFRC / 8 as the input clock.
HFRC_DIV16 = 0x5 - Selects the HFRC / 16 as the input clock.
HFRC_DIV32 = 0x6 - Selects the HFRC / 32 as the input clock.
HFRC_DIV64 = 0x7 - Selects the HFRC / 64 as the input clock.
7:1 RSVD 0x0 RO
RESERVED
0 IOCLKEN 0x0 RW
Enable for the interface clock. Must be enabled prior to executing any IO
operations.
Table 267: CMD Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
OFFSETLO
RSRVD54
CMDSEL
TSIZE
CONT
OFFSETCNT
CMD