User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 185 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
6.3.2.4 FIFOPOP Register
FIFO POP register
OFFSET: 0x00000108
INSTANCE 0 ADDRESS: 0x5000C108
Will advance the internal read pointer of the incoming FIFO (FIFO1) when read, if POPWR is not active. If
POPWR is active, a write to this register is needed to advance the internal FIFO pointer.
6.3.2.5 FIFOPUSH Register
FIFO PUSH register
OFFSET: 0x0000010C
INSTANCE 0 ADDRESS: 0x5000C10C
Will write new data into the outgoing FIFO and advance the internal write pointer.
5:0 FIFORTHR 0x0 RW
FIFO read threshold in bytes. A value of 0 will disable the read FIFO level
from activating the threshold interrupt. If this field is non-zero, it will trigger a
threshold interrupt when the read fifo contains FIFORTHR valid bytes of
data, as indicated by the FIFO1SIZ field. This is intended to signal when a
data transfer of FIFORTHR bytes can be done from the IOM module to the
host via the read fifo to support large IOM read operations.
Table 257: FIFOPOP Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FIFODOUT
Table 258: FIFOPOP Register Bits
Bit Name Reset RW Description
31:0 FIFODOUT 0x0 RW
This register will return the read data indicated by the current read pointer
on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the
fifo read pointer will be advanced by one word as a result of the read.
Table 259: FIFOPUSH Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FIFODIN
Table 256: FIFOTHR Register Bits
Bit Name Reset RW Description