User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 184 of 909 2019 Ambiq Micro, Inc.
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6.3.2.3 FIFOTHR Register
FIFO Threshold Configuration
OFFSET: 0x00000104
INSTANCE 0 ADDRESS: 0x5000C104
Sets the threshold values for incoming and outgoing transactions. The threshold values are used to
assert the interrupt if enabled, and also used during DMA to set the transfer size as a result of DMATHR
trigger.
Table 254: FIFOPTR Register Bits
Bit Name Reset RW Description
31:24 FIFO1REM 0x0 RO
The number of remaining data bytes slots currently in FIFO 1 (written by
interface, read by MCU)
23:16 FIFO1SIZ 0x0 RO
The number of valid data bytes currently in FIFO 1 (written by interface,
read by MCU)
15:8 FIFO0REM 0x0 RO
The number of remaining data bytes slots currently in FIFO 0 (written by
MCU, read by interface)
7:0 FIFO0SIZ 0x0 RO
The number of valid data bytes currently in the FIFO 0 (written by MCU,
read by interface)
Table 255: FIFOTHR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD FIFOWTHR
RSVD
FIFORTHR
Table 256: FIFOTHR Register Bits
Bit Name Reset RW Description
31:14 RSVD 0x0 RO
RESERVED
13:8 FIFOWTHR 0x0 RW
FIFO write threshold in bytes. A value of 0 will disable the write FIFO level
from activating the threshold interrupt. If this field is non-zero, it will trigger a
threshold interrupt when the write fifo contains FIFOWTHR free bytes, as
indicated by the FIFO0REM field. This is intended to signal when a transfer
of FIFOWTHR bytes can be done from the host to the IOM write fifo to sup-
port large IOM write operations.
7:6 RSVD 0x0 RO
RESERVED