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Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 18 of 909 2019 Ambiq Micro, Inc.

Table 183: DBGR1 Register ..................................................................................................... 143

Table 184: DBGR1 Register Bits ............................................................................................. 143

Table 185: DBGR2 Register ..................................................................................................... 143

Table 186: DBGR2 Register Bits ............................................................................................. 143

Table 187: PMUENABLE Register ......................................................................................... 144

Table 188: PMUENABLE Register Bits .................................................................................. 144

Table 189: TPIUCTRL Register ............................................................................................... 144

Table 190: TPIUCTRL Register Bits ....................................................................................... 144

Table 191: OTAPOINTER Register ......................................................................................... 145

Table 192: OTAPOINTER Register Bits ................................................................................. 145

Table 193: APBDMACTRL Register ....................................................................................... 146

Table 194: APBDMACTRL Register Bits ............................................................................... 146

Table 195: SRAMMODE Register ........................................................................................... 147

Table 196: SRAMMODE Register Bits ................................................................................... 147

Table 197: KEXTCLKSEL Register ........................................................................................ 148

Table 198: KEXTCLKSEL Register Bits ................................................................................. 148

Table 199: SIMOBUCK4 Register ........................................................................................... 148

Table 200: SIMOBUCK4 Register Bits ................................................................................... 148

Table 201: BLEBUCK2 Register ............................................................................................. 150

Table 202: BLEBUCK2 Register Bits ...................................................................................... 150

Table 203: FLASHWPROT0 Register ..................................................................................... 150

Table 204: FLASHWPROT0 Register Bits .............................................................................. 151

Table 205: FLASHWPROT1 Register ..................................................................................... 151

Table 206: FLASHWPROT1 Register Bits .............................................................................. 151

Table 207: FLASHRPROT0 Register ...................................................................................... 151

Table 208: FLASHRPROT0 Register Bits ............................................................................... 152

Table 209: FLASHRPROT1 Register ...................................................................................... 152

Table 210: FLASHRPROT1 Register Bits ............................................................................... 152

Table 211: DMASRAMWRITEPROTECT0 Register ............................................................. 152

Table 212: DMASRAMWRITEPROTECT0 Register Bits ..................................................... 153

Table 213: DMASRAMWRITEPROTECT1 Register ............................................................. 153

Table 214: DMASRAMWRITEPROTECT1 Register Bits ..................................................... 153

Table 215: DMASRAMREADPROTECT0 Register ............................................................... 153

Table 216: DMASRAMREADPROTECT0 Register Bits ....................................................... 154

Table 217: DMASRAMREADPROTECT1 Register ............................................................... 154

Table 218: DMASRAMREADPROTECT1 Register Bits ....................................................... 154

Table 219: CACHECTRL Register Map .................................................................................. 159

Table 220: CACHECFG Register ............................................................................................. 160

Table 221: CACHECFG Register Bits ..................................................................................... 160

Table 222: FLASHCFG Register ............................................................................................. 161

Table 223: FLASHCFG Register Bits ...................................................................................... 161

Table 224: CTRL Register ........................................................................................................ 162

Table 225: CTRL Register Bits ................................................................................................ 162

Table 226: NCR0START Register ........................................................................................... 163

Table 227: NCR0START Register Bits .................................................................................... 164

Table 228: NCR0END Register ............................................................................................... 164