User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 172 of 909 2019 Ambiq Micro, Inc.

states and can operate up to the maximum operating frequency of the CPU core. On Apollo3, the DTCM

banks are guaranteed to be zero wait-state unless there is contention for that specific memory array with

another requestor (CPU I/D Bus or DMA Bus). The Main SRAM banks are zero wait-state for sequential

accesses or 1-wait state for non-sequential accesses for I/D Bus accesses unless there is contention for

that specific memory array with another requestor (CPU I/D Bus or DMA Bus). DMA accesses to Main

SRAM are always 0-wait state unless there is contention for that specific memory array. Prefetching is

used on the I/D Bus accesses to Main SRAM to minimize/eliminate wait-state bubbles. Prefetching can be

enabled/disabled for I and/or D Bus accesses.

The Interface contains arbitration logic for each SRAM instance which allows one of 2 bus slaves access to

the SRAM on any given cycle.

Figure 8 shows a logical block diagram of the SRAM Interface.