User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 171 of 909 2019 Ambiq Micro, Inc.

same line should not be exceeded. Doing more than the restricted number of program cycles to the same

line between erase operations may cause data corruption/retention issues within the word line.

3.9.4 SRAM Interface

3.9.4.1 Functional Overview

Figure 8. Block diagram for the SRAM Interface

The SRAM Interface translates requests from the CPU core and DMA controllers to the SRAM Memory

Instances for instruction and data fetches. The SRAM interface is designed to return data in zero wait-

AHB Slave Decoder

Arbiter

DTCM1

SRAM0

SRAM1

SRAM2

SRAM3

SRAM4

Arbiter

SRAM5

Arbiter

SRAM6

Arbiter

SRAM9

AHB Slave Decoder

CPU I-Code Bus

CPU D-Code Bus

DMA Bus

Arbiter

DTCM0

Arbiter

SRAM7

Arbiter

SRAM8