User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 163 of 909 2019 Ambiq Micro, Inc.
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3.9.3.2.2.4NCR0START Register
Flash Cache Noncachable Region 0 Start
OFFSET: 0x00000010
INSTANCE 0 ADDRESS: 0x40018010
Flash Cache Noncachable Region 0 Start
10
FLASH1_SLM_
ENABLE
0x0 WO
Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE:
there is a 5us latency after waking flash until the first access will be
returned.
9
FLASH1_SLM_-
DISABLE
0x0 WO
Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (read-
ing the array will also automatically wake it).
8
FLASH1_SLM_
STATUS
0x0 RO
Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indi-
cates flash1 is in normal mode.
7 RSVD 0x0 RO
This bitfield is reserved for future use.
6
FLASH0_SLM_
ENABLE
0x0 WO
Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE:
there is a 5us latency after waking flash until the first access will be
returned.
5
FLASH0_SLM_-
DISABLE
0x0 WO
Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (read-
ing the array will also automatically wake it).
4
FLASH0_SLM_
STATUS
0x0 RO
Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indi-
cates flash0 is in normal mode.
3 RSVD 0x0 RO
This bitfield is reserved for future use.
2 CACHE_READY 0x0 RO
Cache Ready Status (enabled and not processing an invalidate operation)
1 RESET_STAT 0x0 WO
Reset Cache Statistics. When written to a 1, the cache monitor counters will
be cleared. The monitor counters can be reset only when the
CACHECFG.ENABLE_MONITOR bit is set.
CLEAR = 0x1 - Clear Cache Stats
0INVALIDATE 0x0WO
Writing a 1 to this bitfield invalidates the flash cache contents.
Table 226: NCR0START Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD ADDR RSVD
Table 225: CTRL Register Bits
Bit Name Reset RW Description