User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 158 of 909 2019 Ambiq Micro, Inc.
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3.9.3.1.1 Cache Operation
To enable the cache, software should write the CACHECFG register with the desired setting. The ENABLE
field in this register will power up the cache SRAMs and initiate the cache startup sequence which will flush
the cache RAMs. Once the sequence is complete (indicated by the CACHE_READY bit in the
CACHECTRL register), the cache will automatically begin servicing instruction and/or data fetches from
the cache depending on the state of the ICACHE_ENABLE and DCACHE_ENABLE values. Software can
choose to enable/disable these independently and they can be dynamically changed during operation.
Additionally, the non-cachable region registers can be used to mark regions as non-cached, which
supercedes the I/D enable bits and causes all fetches from within this range to be non-cached.
The cache will automatically flush data contents if flash is erased/programmed or if the primary cache
enable bit is disabled. Additionally, software can invalidate the cache by writing the INVALIDATE bit of the
CACHECTRL register. Since this register contains only status information (on reads) and activates
controls based on bits set, there is no need to perform a read-modify-write.
For any mode changes, the cache should first be disabled by writing the ENABLE bit to 0, changing the
configuration, then re-writing the enable bit to a 1.
3.9.3.1.2 Cache Performance Monitors
The cache also includes logic to monitor cache performance, which should be used in conjunction with the
STIMER or CTIMER to determine elapsed time. The instruction and data buses have independent
monitoring logic that keep counts of the following conditions:
▪ ACCESS_COUNT - total number of reads performed on the bus
▪ LOOKUP_COUNT - number of tag lookups performed
▪ HIT_COUNT - number of tag lookups that result in a hit
▪ LINE_COUNT - number of reads that were serviced from the line buffers (on a miss or non-cached
access) or directly from the RAM because they fell within the same line as the previous lookup.
The LOOKUP and LINE counts should sum to the ACCESS COUNT and the number of cache misses can
be calculated as LOOKUP_COUNT - HIT_COUNT.
NOTE: The DMONn and IMONn registers should be read with the cache monitor disabled (
CACHECFG[ENABLE_MONITOR] = 0x0).
Cache monitor counters will automatically freeze the counts when either of the access counters reaches a
value of 0xFFFF0000 to prevent the counters from rolling over. The monitor counts can be reset at any
time by writing the RESET_STAT bit in the CACHECTRL register.
The monitors do not provide an indication of waitstates added to accesses, so the elapsed time should be
used to infer this value (waitstates are added as a result of cache misses or contention for the tag lookup if
both busses require a simultaneous lookup).
3.9.3.2 CACHECTRL Registers
Flash Cache Controller
INSTANCE 0 BASE ADDRESS:0x40018000