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Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 149 of 909 2019 Ambiq Micro, Inc.

27:26

SIMOBUCKU-

VLOMODE

0x3 RW

simobuck_uvlo_mode. In B0, these bits are used as SIMOBUCK mode bits.

uvlo_mode[0] enables use of tonclk_lp for all operations and uvlo_mode[1]

controls core_low/mem_low synchronization.

USE_LP_CLOCK = 0x1 - LP clock is used for simobuck in both active and

low-power mode.

X_LOW_NOSYNC = 0x2 - No synchronization is applied to core_low/

mem_low inputs (A1 behavior)

X_LOW_SYNC = 0x0 - Synchronization is applied to core_low/mem_low

inputs

SIMOBUCKPRI-

ORITYSEL

0x0 RW

simobuck_priority_sel

SIMOBUCK-

COMP2TIME-

OUTEN

0x0 RW

simobuck_comp2_timeout_en

SIMOBUCK-

COMP2LPEN

0x1 RW

simobuck_comp2_lp_en

22:21

SIMOBUCK-

CLKDIVSEL

0x0 RW

simobuck_clkdiv_sel

SIMOBUCKEX-

TCLKSEL

0x0 RW

simobuck_extclk_sel

19:17

SIMOBUCKU-

VLODRVSTR-

TRIM

0x6 RW

simobuck_uvlo_drvstr_trim

16:14

SIMOBUCKU-

VLOCNTRTRIM

0x6 RW

For B0, this register has been redefined as mode bits for the Simobuck.

Each bit is independent: [0]=always enable LP clock [1]=enable priori-

ty_state [2]=enable zx_comp reset removal fix

ENABLE_LP_CLK = 0x1 - When set to 1, the LP clock will always be acti-

vated. When 0, the logic will request the clock when needed

DISABLE_PRIORITY_STATE = 0x2 - (Inverse polarity mode bit) When set

to 1, the priority state logic will be disabled and when set to 0, priority_state

will enforce that both core and mem bucks get equal priority.

ENABLE_ZXCOMP_SYNC = 0x4 - When set to 1, ZXCOMP will be routed

through a flop and removal synchronized to the internal clock. When set to

0, logic will act like A1 logic and will be asynchronous.

13:10

SIMOBUCKZX-

TRIM

0x0 RW

simobuck_zx_trim

9:8

SIMOBUCK-

MEMLEAKAG-

ETRIM

0x0 RW

simobuck_mem_leakage_trim

7:6

SIMOBUCK-

MEMLP-

DRVSTRTRIM

0x2 RW

simobuck_mem_lp_drvstr_trim

5:4

SIMOBUCKME-

MACTDRVSTR-

TRIM

0x2 RW

simobuck_mem_act_drvstr_trim

3:0

SIMOBUCK-

MEMLPLOW-

TONTRIM

0xa RW

simobuck_mem_lp_low_ton_trim

Table 200: SIMOBUCK4 Register Bits

Bit Name Reset RW Description