User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 146 of 909 2019 Ambiq Micro, Inc.
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3.8.2.32 APBDMACTRL Register
DMA Control Register. Determines misc settings for DMA operation
OFFSET: 0x00000280
INSTANCE 0 ADDRESS: 0x40020280
DMA Control Register. Determines misc settings for DMA operation
0 OTAVALID 0x0 RW
Indicates that an OTA update is valid
Table 193: APBDMACTRL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD HYSTERESIS RSVD
DECODEABORT
DMA_ENABLE
Table 194: APBDMACTRL Register Bits
Bit Name Reset RW Description
31:16 RSVD 0x0 RO
RESERVED.
15:8 HYSTERESIS 0x2 RW
This field determines how long the DMA will remain active during deep
sleep before shutting down and returning the system to full deep sleep. Val-
ues are based on a 94KHz clock and are roughly 10us increments for a
range of ~10us to 2.55ms
7:2 RSVD 0x0 RO
RESERVED.
1
DECODEA-
BORT
0x1 RW
APB Decode Abort. When set, the APB bridge will issue a data abort (bus
fault) on transactions to peripherals that are powered down. When set to 0,
writes are quietly discarded and reads return 0.
DISABLE = 0x0 - Bus operations to powered down peripherals are quietly
discarded
ENABLE = 0x1 - Bus operations to powered down peripherals result in a
bus fault.
0 DMA_ENABLE 0x1 RW
Enable the DMA controller. When disabled, DMA requests will be ignored
by the controller
DISABLE = 0x0 - DMA operations disabled
ENABLE = 0x1 - DMA operations enabled
Table 192: OTAPOINTER Register Bits
Bit Name Reset RW Description